BASIC TRAINING: DIGITAL IC DESIGN WITH ICC SYNOPSYS
17-19 May 2017
Collaborative Microelectronic Design Excellence Centre (CEDEC)
Universiti Sains Malaysia
Level 1, Block C
No. 10 Persiaran Bukit Jambul
11900 Bayan Lepas, Penang.
The IC Compiler (ICC) tool is a single, convergent netlist-to-GDSII or netlist-to-clock-tree-synthesis design tool for chip designers developing very deep submicron designs. It takes as input a gate-level netlist, a detailed floorplan, timing constraints, physical and timing libraries, and foundry-process data, and it generates as output either a GDSII-format file of the layout or a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. The ICC tool can also output the design at any time as a binary Synopsys Milkyway database for use with other Synopsys tools based on Milkyway or as ASCII files (Verilog, DEF, and timing constraints) for use with tools not from Synopsys.
Use ICC to efficiently perform non-hierarchical chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges.
ASIC, back-end or layout designers who will be using ICC for physical design.
- Starting the ICC GUI
- Data setup & basic flow
- Design Planning
- Clock Tree Synthesis
- Chip finishing
|17 May 2017 (Wednesday)||9:30 – 10:30 am||Starting the ICC GUI|
|10.30 – 1 pm||Data setup & basic flow|
|1:00 – 2:00 pm||Lunch break|
|2:00 – 5:00 pm||Cont: Data setup & basic flow|
18 May 2017
|9:30 – 1:00 pm||Design Planning|
|1:00 -2:00 pm||Lunch Break|
|2:00 – 5:00 pm||Placement|
19 May 2017
|9:30 – 10:30 am||Clock Tree Synthesis|
|10.30 – 12.30 pm||Routing|
|12.30 – 2.45 pm||Lunch Break|
|2.45 – 5:00 pm||Chip Finishing|